Radiation hardened RISC-V processor
This thesis focuses on designing and validating an open-source 32-bit RISC-V processor and implementing using NTU’s in-house RHBD cell library. We inves tigate, analyse and compare the final layout in timing, area, and power based on three different libraries: (a) Full triple-module-redundancy (T...
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| Other Authors: | |
| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2022
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| Online Access: | https://hdl.handle.net/10356/156208 |
| _version_ | 1811691418072121344 |
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| author | Gu, Haoteng |
| author2 | Chang Joseph |
| author_facet | Chang Joseph Gu, Haoteng |
| author_sort | Gu, Haoteng |
| collection | NTU |
| description | This thesis focuses on designing and validating an open-source 32-bit RISC-V
processor and implementing using NTU’s in-house RHBD cell library. We inves tigate, analyse and compare the final layout in timing, area, and power based on
three different libraries:
(a) Full triple-module-redundancy (TMR) technique using the GF 65nm library
(b) DICE library
(c) NTU’s in-house library
The results show that the RHBD RISC-V design using NTU’s in-house library
passes functional tests at 250MHz, and can run higher if a faster SRAM is used.
This suggests that NTU’s in-house library is applicable for high-speed applica tions.
The results also show that the implementation using our in-house library is about
33% smaller than the implementation using DICE and about 60% smaller than
the implementation applying full TMR using the GF 65nm library. In terms
of power consumption, the implementation using our in-house library is almost
equal to the implementation using the DICE library and 30% smaller than the
implementation applying full TMR in the worst case.
Overall, in the implementation of the RHBD RISC-V processor, we conclude that
the application of NTU’s in-house RHBD library is superior to reported RHBD
methodologies, including DICE and TMR. |
| first_indexed | 2024-10-01T06:19:34Z |
| format | Thesis-Master by Coursework |
| id | ntu-10356/156208 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:19:34Z |
| publishDate | 2022 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1562082023-07-04T17:51:28Z Radiation hardened RISC-V processor Gu, Haoteng Chang Joseph School of Electrical and Electronic Engineering EJSCHANG@ntu.edu.sg Engineering::Electrical and electronic engineering This thesis focuses on designing and validating an open-source 32-bit RISC-V processor and implementing using NTU’s in-house RHBD cell library. We inves tigate, analyse and compare the final layout in timing, area, and power based on three different libraries: (a) Full triple-module-redundancy (TMR) technique using the GF 65nm library (b) DICE library (c) NTU’s in-house library The results show that the RHBD RISC-V design using NTU’s in-house library passes functional tests at 250MHz, and can run higher if a faster SRAM is used. This suggests that NTU’s in-house library is applicable for high-speed applica tions. The results also show that the implementation using our in-house library is about 33% smaller than the implementation using DICE and about 60% smaller than the implementation applying full TMR using the GF 65nm library. In terms of power consumption, the implementation using our in-house library is almost equal to the implementation using the DICE library and 30% smaller than the implementation applying full TMR in the worst case. Overall, in the implementation of the RHBD RISC-V processor, we conclude that the application of NTU’s in-house RHBD library is superior to reported RHBD methodologies, including DICE and TMR. Master of Science (Integrated Circuit Design) 2022-04-07T01:20:56Z 2022-04-07T01:20:56Z 2022 Thesis-Master by Coursework Gu, H. (2022). Radiation hardened RISC-V processor. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/156208 https://hdl.handle.net/10356/156208 en application/pdf Nanyang Technological University |
| spellingShingle | Engineering::Electrical and electronic engineering Gu, Haoteng Radiation hardened RISC-V processor |
| title | Radiation hardened RISC-V processor |
| title_full | Radiation hardened RISC-V processor |
| title_fullStr | Radiation hardened RISC-V processor |
| title_full_unstemmed | Radiation hardened RISC-V processor |
| title_short | Radiation hardened RISC-V processor |
| title_sort | radiation hardened risc v processor |
| topic | Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/156208 |
| work_keys_str_mv | AT guhaoteng radiationhardenedriscvprocessor |