A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector

A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector

The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer-N phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth...

Full description

Bibliographic Details
Main Authors: Liang, Yuan, Boon, Chirn Chye
Other Authors: School of Electrical and Electronic Engineering
Format: Journal Article
Language:English
Published: 2022
Subjects:
Engineering::Electrical and electronic engineering::Integrated circuits
Integrated Jitter
CMOS Phase-Locked Loop
Online Access:https://hdl.handle.net/10356/156845

Internet

https://hdl.handle.net/10356/156845

Similar Items