A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector
The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer-N phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth...
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| Format: | Journal Article |
| Language: | English |
| Published: |
2022
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| Online Access: | https://hdl.handle.net/10356/156845 |
| _version_ | 1811682969109135360 |
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| author | Liang, Yuan Boon, Chirn Chye |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Liang, Yuan Boon, Chirn Chye |
| author_sort | Liang, Yuan |
| collection | NTU |
| description | The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer-N phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection and lock detection. Implemented in 40-nm CMOS technology, the proposed PLL shows a -75-dBc reference spur, -101.5-dBc/Hz PN at a 1-MHz offset, and a minimum integrated jitter of 121.9 fs <formula> <tex>$_{{rms}}$</tex> </formula> (10 kHz-100 MHz) at 38.2 GHz with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of -245 dB. |
| first_indexed | 2024-10-01T04:05:17Z |
| format | Journal Article |
| id | ntu-10356/156845 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T04:05:17Z |
| publishDate | 2022 |
| record_format | dspace |
| spelling | ntu-10356/1568452022-06-10T07:00:47Z A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector Liang, Yuan Boon, Chirn Chye School of Electrical and Electronic Engineering VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering::Integrated circuits Integrated Jitter CMOS Phase-Locked Loop The high phase noise (PN) of CMOS millimeter-wave oscillators has encouraged the adoption of wide loop bandwidth for an integer-N phase-locked loop (PLL). This article proposes a quadrature sampling phase-frequency detector (QS-PFD) to disengage the tradeoff between spur rejection and loop bandwidth. With the introduction of an auxiliary path for phase detection, the spur generated by the main path is canceled without incurring extra power or degrading the loop stability. The high gain of the QS-PFD attenuates its jitter contribution to the loop. The QS-PFD enables fast frequency detection and lock detection. Implemented in 40-nm CMOS technology, the proposed PLL shows a -75-dBc reference spur, -101.5-dBc/Hz PN at a 1-MHz offset, and a minimum integrated jitter of 121.9 fs <formula> <tex>$_{{rms}}$</tex> </formula> (10 kHz-100 MHz) at 38.2 GHz with a division ratio of 128. The lock detection time is at the microsecond level. The proposed PLL consumes 23.6 mW from a 1.1-V power supply, leading to a figure of merit (FoM) of -245 dB. Ministry of Education (MOE) Submitted/Accepted version This work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 under Grant MOE2019-T2-1-114. 2022-04-28T02:08:55Z 2022-04-28T02:08:55Z 2022 Journal Article Liang, Y. & Boon, C. C. (2022). A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector. IEEE Transactions On Microwave Theory and Techniques, 70(4), 2299-2314. https://dx.doi.org/10.1109/TMTT.2022.3148427 0018-9480 https://hdl.handle.net/10356/156845 10.1109/TMTT.2022.3148427 2-s2.0-85125361066 4 70 2299 2314 en MOE2019-T2-1-114 IEEE Transactions on Microwave Theory and Techniques © 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/TMTT.2022.3148427. application/pdf |
| spellingShingle | Engineering::Electrical and electronic engineering::Integrated circuits Integrated Jitter CMOS Phase-Locked Loop Liang, Yuan Boon, Chirn Chye A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector |
| title | A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector |
| title_full | A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector |
| title_fullStr | A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector |
| title_full_unstemmed | A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector |
| title_short | A 40 GHz CMOS PLL with -75-dBc reference spur and 121.9-fs rms jitter featuring a quadrature sampling phase-frequency detector |
| title_sort | 40 ghz cmos pll with 75 dbc reference spur and 121 9 fs rms jitter featuring a quadrature sampling phase frequency detector |
| topic | Engineering::Electrical and electronic engineering::Integrated circuits Integrated Jitter CMOS Phase-Locked Loop |
| url | https://hdl.handle.net/10356/156845 |
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