A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector

A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector

This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer-N phaselocked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs...

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Bibliographic Details
Main Authors: Liang, Yuan, Boon, Chirn Chye, Chen, Qian
Other Authors: School of Electrical and Electronic Engineering
Format: Journal Article
Language:English
Published: 2022
Subjects:
Engineering::Electrical and electronic engineering::Integrated circuits
CMOS Phase-Locked Loop
Phase Detector
Online Access:https://hdl.handle.net/10356/156847

Internet

https://hdl.handle.net/10356/156847

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