A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector
This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer-N phaselocked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2022
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/156847 |
| _version_ | 1826124881058594816 |
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| author | Liang, Yuan Boon, Chirn Chye Chen, Qian |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Liang, Yuan Boon, Chirn Chye Chen, Qian |
| author_sort | Liang, Yuan |
| collection | NTU |
| description | This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer-N phaselocked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB. |
| first_indexed | 2024-10-01T06:27:37Z |
| format | Journal Article |
| id | ntu-10356/156847 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:27:37Z |
| publishDate | 2022 |
| record_format | dspace |
| spelling | ntu-10356/1568472023-01-16T07:41:01Z A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector Liang, Yuan Boon, Chirn Chye Chen, Qian School of Electrical and Electronic Engineering VIRTUS, IC Design Centre of Excellence Engineering::Electrical and electronic engineering::Integrated circuits CMOS Phase-Locked Loop Phase Detector This letter introduces a novel phase detector (PD) for suppressing the reference spur in a 40 GHz integer-N phaselocked loop (PLL). Coined as a spur-compensation phase detector (SCPD), the proposed SCPD duplicates itself to an auxiliary path for an edge-combined phase alignment, such that the spurs generated by the two paths mutually compensate for each other, achieving a net effect of spur canceling. Implemented in a 40-nm CMOS technology, the proposed PLL shows less than −71.4-dBc reference spur, −98- and −117-dBc/Hz phase noise at 1- and 10-MHz offset, respectively, and a minimum rms jitter of 114 fs (10 k–100 MHz). It consumes 23.4-mW power from a 1.1-V power supply, leading to a figure of merit (FoM) of −245 dB. Ministry of Education (MOE) Submitted/Accepted version This work was supported by the Singapore Ministry of Education Academic Research Fund Tier 2 under Grant MOE2019-T2-1-114. 2022-04-28T02:35:11Z 2022-04-28T02:35:11Z 2022 Journal Article Liang, Y., Boon, C. C. & Chen, Q. (2022). A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector. IEEE Microwave and Wireless Components Letters, 32(9), 1091-1094. https://dx.doi.org/10.1109/LMWC.2022.3153326 1531-1309 https://hdl.handle.net/10356/156847 10.1109/LMWC.2022.3153326 9 32 1091 1094 en MOE2019-T2-1-114 IEEE Microwave and Wireless Components Letters © 2022 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. The published version is available at: https://doi.org/10.1109/LMWC.2022.3153326. application/pdf |
| spellingShingle | Engineering::Electrical and electronic engineering::Integrated circuits CMOS Phase-Locked Loop Phase Detector Liang, Yuan Boon, Chirn Chye Chen, Qian A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector |
| title | A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector |
| title_full | A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector |
| title_fullStr | A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector |
| title_full_unstemmed | A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector |
| title_short | A 23.4 mW -72-dBc reference spur 40 GHz CMOS PLL featuring a spur-compensation phase detector |
| title_sort | 23 4 mw 72 dbc reference spur 40 ghz cmos pll featuring a spur compensation phase detector |
| topic | Engineering::Electrical and electronic engineering::Integrated circuits CMOS Phase-Locked Loop Phase Detector |
| url | https://hdl.handle.net/10356/156847 |
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