Design of a low noise low voltage preamplifier
A low noise low voltage preamplifier is designed in this project. Using a 0.18 μm CMOS technology, a two-stage CMOS folded cascode operational amplifier with class AB output buffer is designed utilizing Cadence Custom IC Design Tool. The preamplifier is biased by a constant-transconductance bias cir...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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2009
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| Online Access: | http://hdl.handle.net/10356/15705 |