LTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arrays
RRAM, which has the characteristics of high speed, low power consumption, easy integration, compatibility with CMOS technology, is a potential NVM technology. It is considered as the next-generation high density storage and high-performance computing technology, and also, a powerful alternative of f...
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| Format: | Thesis-Master by Coursework |
| Language: | English |
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Nanyang Technological University
2022
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| Online Access: | https://hdl.handle.net/10356/159456 |
| _version_ | 1826121644156911616 |
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| author | Du, Yifan |
| author2 | Chen Tupei |
| author_facet | Chen Tupei Du, Yifan |
| author_sort | Du, Yifan |
| collection | NTU |
| description | RRAM, which has the characteristics of high speed, low power consumption, easy integration, compatibility with CMOS technology, is a potential NVM technology. It is considered as the next-generation high density storage and high-performance computing technology, and also, a powerful alternative of flash memory technology.
In this dissertation, we first briefly reviewed several mainstream memory technologies, including the volatile memory (or random access memory) technologies represented by SRAM and DRAM and the non-volatile memory technology represented by flash memory. Aiming at many shortcomings of flash technology, we listed three NMV technologies which are considered as alternatives to traditional NAND and NOR flash memory, including PCRAM, STT-MRAM and RRAM. In chapter 2, we discussed the basic principles of RRAM, especially the memristor, which is a fourth class of electrical circuit, joining the resistor, the capacitor, and the inductor. Also we briefly analyzed how different memristor or electrode materials and RRAM cell structures affect performance. In chapter 3 we built models based on Stanford-PKU RRAM model and 0.18um TSMC N-MOSFET. The simulation results of the RRAM cell model, the 1T1R RRAM structure model and 1T1R RRAM array model are analyzed in chapter 4. Based on the simulation results, methods are proposed to solve the problem occurring during the SPICE code running with the LTspice simulator. |
| first_indexed | 2024-10-01T05:35:35Z |
| format | Thesis-Master by Coursework |
| id | ntu-10356/159456 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:35:35Z |
| publishDate | 2022 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1594562023-07-04T17:51:05Z LTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arrays Du, Yifan Chen Tupei School of Electrical and Electronic Engineering EChenTP@ntu.edu.sg Engineering::Electrical and electronic engineering::Electronic circuits RRAM, which has the characteristics of high speed, low power consumption, easy integration, compatibility with CMOS technology, is a potential NVM technology. It is considered as the next-generation high density storage and high-performance computing technology, and also, a powerful alternative of flash memory technology. In this dissertation, we first briefly reviewed several mainstream memory technologies, including the volatile memory (or random access memory) technologies represented by SRAM and DRAM and the non-volatile memory technology represented by flash memory. Aiming at many shortcomings of flash technology, we listed three NMV technologies which are considered as alternatives to traditional NAND and NOR flash memory, including PCRAM, STT-MRAM and RRAM. In chapter 2, we discussed the basic principles of RRAM, especially the memristor, which is a fourth class of electrical circuit, joining the resistor, the capacitor, and the inductor. Also we briefly analyzed how different memristor or electrode materials and RRAM cell structures affect performance. In chapter 3 we built models based on Stanford-PKU RRAM model and 0.18um TSMC N-MOSFET. The simulation results of the RRAM cell model, the 1T1R RRAM structure model and 1T1R RRAM array model are analyzed in chapter 4. Based on the simulation results, methods are proposed to solve the problem occurring during the SPICE code running with the LTspice simulator. Master of Science (Electronics) 2022-06-20T04:48:06Z 2022-06-20T04:48:06Z 2022 Thesis-Master by Coursework Du, Y. (2022). LTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arrays. Master's thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/159456 https://hdl.handle.net/10356/159456 en application/pdf Nanyang Technological University |
| spellingShingle | Engineering::Electrical and electronic engineering::Electronic circuits Du, Yifan LTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arrays |
| title | LTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arrays |
| title_full | LTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arrays |
| title_fullStr | LTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arrays |
| title_full_unstemmed | LTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arrays |
| title_short | LTspice implementation of PKU compact model of metal-oxide-based RRAM: part C_simulation of RRAM memory arrays |
| title_sort | ltspice implementation of pku compact model of metal oxide based rram part c simulation of rram memory arrays |
| topic | Engineering::Electrical and electronic engineering::Electronic circuits |
| url | https://hdl.handle.net/10356/159456 |
| work_keys_str_mv | AT duyifan ltspiceimplementationofpkucompactmodelofmetaloxidebasedrrampartcsimulationofrrammemoryarrays |