A formal methodology for verifying side-channel vulnerabilities in cache architectures
Security-aware CPU caches have been designed to mitigate side-channel attacks and prevent information leakage. How to validate the effectiveness of these designs remains an unsolved problem. Prior works assess the security of architectures empirically without a formal guarantee, making the evaluatio...
| Main Authors: | , , , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2023
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/165417 |