Energy-efficient hardware accelerators based on bit-serial graph and memory-centric computing architectures
As semiconductor process technology nodes have shrunk over the past few decades, the complexity of application-specific integrated circuits (ASICs) has grown significantly. Emerging ASICs have been widely explored to accelerate various algorithms with high energy efficiency, including machine learni...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis-Doctor of Philosophy |
| Language: | English |
| Published: |
Nanyang Technological University
2023
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/165577 |