Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression

Efficient FPGA-based sparse matrix-vector multiplication with data reuse-aware compression

Sparse matrix-vector multiplication (SpMV) on FPGAs has gained much attention. The performance of SpMV is mainly determined by the number of multiplications between non-zero matrix elements and the corresponding vector values per cycle. On the one side, the off-chip memory bandwidth limits the numbe...

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Bibliografski detalji
Glavni autori: Li, Shiqing, Liu, Di, Liu, Weichen
Daljnji autori: School of Computer Science and Engineering
Format: Journal Article
Jezik:English
Izdano: 2023
Teme:
Engineering::Computer science and engineering
Engineering::Computer science and engineering::Hardware
SpMV
FPGA
Data Reuse
Throughput
Online pristup:https://hdl.handle.net/10356/169152

Internet

https://hdl.handle.net/10356/169152

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