Design of a 800-MHZ PLL in 28NM CMOS technology

Design of a 800-MHZ PLL in 28NM CMOS technology

This dissertation proposes a type–two analog PLL based on charge pump with division ratio of 20 and output frequency of up to 0.8GHz, which has been validated in 28nm CMOS technology system. The input signal is passed through a classic type–four phase and frequency detector, and then the current cha...

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Bibliographic Details
Main Author: Tao, Weiran
Other Authors: Goh Wang Ling
Format: Thesis-Master by Coursework
Language:English
Published: Nanyang Technological University 2024
Subjects:
Engineering
28nm CMOS
Type–two charge pump PLL
Type–four PFD
Cascaded differential LC–VCO
Adjustable digital divider
Rail–to–rail output voltage
Low mismatch, spur and noise
Online Access:https://hdl.handle.net/10356/175977

Internet

https://hdl.handle.net/10356/175977

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