Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU

Hardware acceleration for non-linear layers of transformer networks on RISC-V CPU

This paper explores the utilization of hardware acceleration techniques for the non-linear layers in Transformer networks, specifically within the context of RISC-V CPU archi- tectures. The growing complexity of Transformer-based models, highlighted by their significant computational demands, unders...

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Bibliographic Details
Main Author: Seenivasagan Haresh
Other Authors: Chang Chip Hong
Format: Final Year Project (FYP)
Language:English
Published: Nanyang Technological University 2024
Subjects:
Engineering
Hardware acceleration
RISC-V
Transformers
Online Access:https://hdl.handle.net/10356/177093

Internet

https://hdl.handle.net/10356/177093

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