Hardware accelerator for feature matching with binary search tree

Hardware accelerator for feature matching with binary search tree

Feature matching is an essential step for autonomous robot to localize itself during navigation. However, it is often difficult to achieve the matching in real-time due to limited on-board computing resources. We present an FPGA implementation for stream-processing based feature matching called Bina...

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Bibliographic Details
Main Authors: Thathsara, Miyuru, Lam, Siew-Kei, Kawshan, Damith, Piyasena, Duvindu
Other Authors: College of Computing and Data Science
Format: Conference Paper
Language:English
Published: 2024
Subjects:
Computer and Information Science
Feature matching
FPGA
Binary search tree
Hardware acceleration
Online Access:https://hdl.handle.net/10356/179622

Internet

https://hdl.handle.net/10356/179622

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