A high-resolution discrete-time second-order ΣΔ ADC with improved tolerance to KT/C noise using low oversampling ratio

A high-resolution discrete-time second-order ΣΔ ADC with improved tolerance to KT/C noise using low oversampling ratio

This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the...

Full description

Bibliographic Details
Main Authors: An, Kyung-Chan, Narasimman, Neelakantan, Kim, Tony Tae-Hyoung
Other Authors: School of Electrical and Electronic Engineering
Format: Journal Article
Language:English
Published: 2024
Subjects:
Engineering
Oversampling ADC
High resolution
Online Access:https://hdl.handle.net/10356/180463

Internet

https://hdl.handle.net/10356/180463

Similar Items