Design and analysis of robust sensing schemes for resisitive memory
Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furt...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis-Doctor of Philosophy |
| Language: | English |
| Published: |
Nanyang Technological University
2024
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/181559 |
| _version_ | 1826124960594132992 |
|---|---|
| author | An, Byungkwon |
| author2 | Kim Tae Hyoung |
| author_facet | Kim Tae Hyoung An, Byungkwon |
| author_sort | An, Byungkwon |
| collection | NTU |
| description | Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation.
This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation.
This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin.
This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA).
The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode. |
| first_indexed | 2025-03-09T13:54:33Z |
| format | Thesis-Doctor of Philosophy |
| id | ntu-10356/181559 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2025-03-09T13:54:33Z |
| publishDate | 2024 |
| publisher | Nanyang Technological University |
| record_format | dspace |
| spelling | ntu-10356/1815592025-01-02T10:18:25Z Design and analysis of robust sensing schemes for resisitive memory An, Byungkwon Kim Tae Hyoung School of Electrical and Electronic Engineering VIRTUS, IC Design Centre of Excellence THKIM@ntu.edu.sg Engineering Resistive random-access memory (RRAM) Sensing scheme Emerging non-volatile memories (eNVMs) Resistance ratio (R-Ratio) Resistive memory Time-based sensing scheme Hybrid cell-to-cell comparison-based sensing scheme Non-volatile memories Computing in memory (CIM) Multiply-and-accumulate (MAC) Phase-change random access memory (PRAM) Spin-transfer torque magnetic random-access memory (STT-RAM) Memory integrated circuit Multi-level cells (MLC) Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode. Doctor of Philosophy 2024-12-09T08:53:50Z 2024-12-09T08:53:50Z 2024 Thesis-Doctor of Philosophy An, B. (2024). Design and analysis of robust sensing schemes for resisitive memory. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/181559 https://hdl.handle.net/10356/181559 10.32657/10356/181559 en This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License (CC BY-NC 4.0). application/pdf Nanyang Technological University |
| spellingShingle | Engineering Resistive random-access memory (RRAM) Sensing scheme Emerging non-volatile memories (eNVMs) Resistance ratio (R-Ratio) Resistive memory Time-based sensing scheme Hybrid cell-to-cell comparison-based sensing scheme Non-volatile memories Computing in memory (CIM) Multiply-and-accumulate (MAC) Phase-change random access memory (PRAM) Spin-transfer torque magnetic random-access memory (STT-RAM) Memory integrated circuit Multi-level cells (MLC) An, Byungkwon Design and analysis of robust sensing schemes for resisitive memory |
| title | Design and analysis of robust sensing schemes for resisitive memory |
| title_full | Design and analysis of robust sensing schemes for resisitive memory |
| title_fullStr | Design and analysis of robust sensing schemes for resisitive memory |
| title_full_unstemmed | Design and analysis of robust sensing schemes for resisitive memory |
| title_short | Design and analysis of robust sensing schemes for resisitive memory |
| title_sort | design and analysis of robust sensing schemes for resisitive memory |
| topic | Engineering Resistive random-access memory (RRAM) Sensing scheme Emerging non-volatile memories (eNVMs) Resistance ratio (R-Ratio) Resistive memory Time-based sensing scheme Hybrid cell-to-cell comparison-based sensing scheme Non-volatile memories Computing in memory (CIM) Multiply-and-accumulate (MAC) Phase-change random access memory (PRAM) Spin-transfer torque magnetic random-access memory (STT-RAM) Memory integrated circuit Multi-level cells (MLC) |
| url | https://hdl.handle.net/10356/181559 |
| work_keys_str_mv | AT anbyungkwon designandanalysisofrobustsensingschemesforresisitivememory |