Feasibility studies of high data rate ADC
In the design project, a 2-bit flash ADC stage has been developed. All the functional blocks are investigated and optimized according the design specifications. The proposed fully differential double-sampled sample and hold circuit with low pedestal error and a fully differential dynamic latch compa...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2009
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/18375 |