Wire level encapsulation framework for increasing FPGA design productivity
This thesis explores the performance impact of optimising the components of a Field Programmable Gate Array (FPGA) system down to the lowest level independently from other parts of the system. The motivation for this is that not only is the design and verification effort put in to a component reused...
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| Format: | Thesis |
| Language: | English |
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2009
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| Online Access: | https://hdl.handle.net/10356/19266 |