Low-power techniques for CMOS SRAM design
This project attempts on exploring some low-power circuit techniques for CMOS SRAM design. The interests of this work are focused on the power reduction of the memory cell array, current-mode sensing circuit and FIFO memory.
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| Format: | Thesis |
| Language: | English |
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2009
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| Online Access: | http://hdl.handle.net/10356/19581 |