Design and implementation of a high speed chess move generator

This thesis describes the design and implementation of high speed hardware chess modules which can be used to form a complete high speed chess machine. It describes how the large task of computer chess was parallelized and implemented on a field programmable gate array (FPGA) platform. The main modu...

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Bibliographic Details
Main Author: Jaya Shankar Pathmasuntharam
Other Authors: Goh, Wee Leng
Format: Thesis
Language:English
Published: 2009
Subjects:
Online Access:http://hdl.handle.net/10356/19623