Delay sensitivity analysis of scaled BiCMOS/CMOS/ECL circuits
The speed sensitivity of the BiCMOS, CMOS and ECL inverter circuits to changes in the key MOS/BJT device parameters is analyzed. The study of BiCMOS circuit takes into account the changes in the forward transit time, the knee current, the collector resistance, the base resistance, and the current ga...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
2009
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/19686 |