FPGA implementation of turbo decoders with various decoding algorithms
This thesis is aimed to implement turbo decoder with various iteratie decoding algorithms, and to compare their hardware requirements, speeds achievable and error performances.
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Published: |
2008
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/2385 |