High speed, low jitter CMOS analog PLL for clock recovery application
This thesis presents a CMOS PLL differential design techniques for whole PLL systems in order to reject supply-coupled noise. Apart from the supply coupled noise, there are other issues in the PLL systems such as closed loop bandwidth requirements, reduction of the VCO phase noise through appropriat...
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| Format: | Thesis |
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2008
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| Online Access: | http://hdl.handle.net/10356/3294 |