Source line resistance failure issues and process optimisation of self aligned source etch
A self-aligned source oxide etch recipe using low power recipe was changed to higher power recipe to improve production cycle time (due to higher etch rate) and resolve plasma un-ignition. However, some lots started to fail with higher source line resistance during electrical testing.
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| Other Authors: | |
| Format: | Thesis |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/3297 |
| _version_ | 1811682420541358080 |
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| author | Su, Julia Hui Fong. |
| author2 | Prasad, Krishnamachar |
| author_facet | Prasad, Krishnamachar Su, Julia Hui Fong. |
| author_sort | Su, Julia Hui Fong. |
| collection | NTU |
| description | A self-aligned source oxide etch recipe using low power recipe was changed to higher power recipe to improve production cycle time (due to higher etch rate) and resolve plasma un-ignition. However, some lots started to fail with higher source line resistance during electrical testing. |
| first_indexed | 2024-10-01T03:56:33Z |
| format | Thesis |
| id | ntu-10356/3297 |
| institution | Nanyang Technological University |
| last_indexed | 2024-10-01T03:56:33Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | ntu-10356/32972023-07-04T16:05:38Z Source line resistance failure issues and process optimisation of self aligned source etch Su, Julia Hui Fong. Prasad, Krishnamachar School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Microelectronics A self-aligned source oxide etch recipe using low power recipe was changed to higher power recipe to improve production cycle time (due to higher etch rate) and resolve plasma un-ignition. However, some lots started to fail with higher source line resistance during electrical testing. Master of Science (Microelectronics) 2008-09-17T09:26:47Z 2008-09-17T09:26:47Z 2004 2004 Thesis http://hdl.handle.net/10356/3297 Nanyang Technological University application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Microelectronics Su, Julia Hui Fong. Source line resistance failure issues and process optimisation of self aligned source etch |
| title | Source line resistance failure issues and process optimisation of self aligned source etch |
| title_full | Source line resistance failure issues and process optimisation of self aligned source etch |
| title_fullStr | Source line resistance failure issues and process optimisation of self aligned source etch |
| title_full_unstemmed | Source line resistance failure issues and process optimisation of self aligned source etch |
| title_short | Source line resistance failure issues and process optimisation of self aligned source etch |
| title_sort | source line resistance failure issues and process optimisation of self aligned source etch |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Microelectronics |
| url | http://hdl.handle.net/10356/3297 |
| work_keys_str_mv | AT sujuliahuifong sourcelineresistancefailureissuesandprocessoptimisationofselfalignedsourceetch |