Layout design for input/output transistors
In this project, the performance of area-efficient CMOS buffers using the octagon-type and circle-type layout for both NMOS and PMOS transistors are investigated. The performance criteria include the efficient use of layout area, output driving/ sinking capability and ESD robustness.
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| Other Authors: | |
| Format: | Thesis |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/3757 |
| _version_ | 1811693525286256640 |
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| author | Wong, David Wing Fatt. |
| author2 | Yeo, Kiat Seng |
| author_facet | Yeo, Kiat Seng Wong, David Wing Fatt. |
| author_sort | Wong, David Wing Fatt. |
| collection | NTU |
| description | In this project, the performance of area-efficient CMOS buffers using the octagon-type and circle-type layout for both NMOS and PMOS transistors are investigated. The performance criteria include the efficient use of layout area, output driving/ sinking capability and ESD robustness. |
| first_indexed | 2024-10-01T06:53:04Z |
| format | Thesis |
| id | ntu-10356/3757 |
| institution | Nanyang Technological University |
| last_indexed | 2024-10-01T06:53:04Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | ntu-10356/37572023-07-04T15:21:36Z Layout design for input/output transistors Wong, David Wing Fatt. Yeo, Kiat Seng School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits In this project, the performance of area-efficient CMOS buffers using the octagon-type and circle-type layout for both NMOS and PMOS transistors are investigated. The performance criteria include the efficient use of layout area, output driving/ sinking capability and ESD robustness. Master of Science (Consumer Electronics) 2008-09-17T09:36:55Z 2008-09-17T09:36:55Z 2001 2001 Thesis http://hdl.handle.net/10356/3757 Nanyang Technological University application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Wong, David Wing Fatt. Layout design for input/output transistors |
| title | Layout design for input/output transistors |
| title_full | Layout design for input/output transistors |
| title_fullStr | Layout design for input/output transistors |
| title_full_unstemmed | Layout design for input/output transistors |
| title_short | Layout design for input/output transistors |
| title_sort | layout design for input output transistors |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| url | http://hdl.handle.net/10356/3757 |
| work_keys_str_mv | AT wongdavidwingfatt layoutdesignforinputoutputtransistors |