Power optimization in data path allocation for high-level synthesis
This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits.
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| Other Authors: | |
| Format: | Thesis |
| Published: |
2008
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| Online Access: | http://hdl.handle.net/10356/4049 |
| _version_ | 1826120184597839872 |
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| author | Zheng, Yuhong. |
| author2 | Jong, Ching Chuen |
| author_facet | Jong, Ching Chuen Zheng, Yuhong. |
| author_sort | Zheng, Yuhong. |
| collection | NTU |
| description | This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits. |
| first_indexed | 2024-10-01T05:12:22Z |
| format | Thesis |
| id | ntu-10356/4049 |
| institution | Nanyang Technological University |
| last_indexed | 2024-10-01T05:12:22Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | ntu-10356/40492023-07-04T15:20:37Z Power optimization in data path allocation for high-level synthesis Zheng, Yuhong. Jong, Ching Chuen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Power electronics This thesis addresses the problem of minimizing power consumption in the high-level synthesis of data-dominated CMOS circuits. Master of Engineering 2008-09-17T09:43:13Z 2008-09-17T09:43:13Z 2001 2001 Thesis http://hdl.handle.net/10356/4049 Nanyang Technological University application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Power electronics Zheng, Yuhong. Power optimization in data path allocation for high-level synthesis |
| title | Power optimization in data path allocation for high-level synthesis |
| title_full | Power optimization in data path allocation for high-level synthesis |
| title_fullStr | Power optimization in data path allocation for high-level synthesis |
| title_full_unstemmed | Power optimization in data path allocation for high-level synthesis |
| title_short | Power optimization in data path allocation for high-level synthesis |
| title_sort | power optimization in data path allocation for high level synthesis |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Power electronics |
| url | http://hdl.handle.net/10356/4049 |
| work_keys_str_mv | AT zhengyuhong poweroptimizationindatapathallocationforhighlevelsynthesis |