FPGA implementation of a speech coder
In this project, one of the speech compression methods, a LPC 10 decoder was designed by using VHDL. In the designed LPC decoder, two different types of speech production model were designed and used to compare their performances. The first model used two adders, two multipliers and one substractor...
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| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2010
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| Online Access: | http://hdl.handle.net/10356/40567 |