Novel transistor structures for future deep submicron MOS applications
Bulk silicon CMOS processing is reaching the limits in device scaling and fabrication. Silicon-an-Insulator (Sal) technology provides an alternative. It not only allows better scalability but also a solution to low power and high performance applications for next generation CMOS devices. Fully deple...
| 第一著者: | |
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| その他の著者: | |
| フォーマット: | 学位論文 |
| 言語: | English |
| 出版事項: |
2010
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| 主題: | |
| オンライン･アクセス: | https://hdl.handle.net/10356/41403 |
| _version_ | 1826124103691534336 |
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| author | Theng, Ah Leong |
| author2 | Goh Wang Ling |
| author_facet | Goh Wang Ling Theng, Ah Leong |
| author_sort | Theng, Ah Leong |
| collection | NTU |
| description | Bulk silicon CMOS processing is reaching the limits in device scaling and fabrication. Silicon-an-Insulator (Sal) technology provides an alternative. It not only allows better scalability but also a solution to low power and high performance applications for next generation CMOS devices. Fully depleted SOI transistors have emerged as one of the leading candidate for CMOS scaling. The possibility of using the back gate has sparked research activities in the field of novel non-classical SOI devices. In recent years, non-classical sal devices such as double, triple and quadruple multi-gate MOSFET have attracted vast interests in various research bodies and researchers. |
| first_indexed | 2024-10-01T06:15:11Z |
| format | Thesis |
| id | ntu-10356/41403 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:15:11Z |
| publishDate | 2010 |
| record_format | dspace |
| spelling | ntu-10356/414032023-07-04T16:53:19Z Novel transistor structures for future deep submicron MOS applications Theng, Ah Leong Goh Wang Ling School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Bulk silicon CMOS processing is reaching the limits in device scaling and fabrication. Silicon-an-Insulator (Sal) technology provides an alternative. It not only allows better scalability but also a solution to low power and high performance applications for next generation CMOS devices. Fully depleted SOI transistors have emerged as one of the leading candidate for CMOS scaling. The possibility of using the back gate has sparked research activities in the field of novel non-classical SOI devices. In recent years, non-classical sal devices such as double, triple and quadruple multi-gate MOSFET have attracted vast interests in various research bodies and researchers. MASTER OF ENGINEERING (EEE) 2010-07-02T04:49:50Z 2010-07-02T04:49:50Z 2008 2008 Thesis Theng, A. L. (2008). Novel transistor structures for future deep submicron MOS applications. Master’s thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/41403 10.32657/10356/41403 en 108 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits Theng, Ah Leong Novel transistor structures for future deep submicron MOS applications |
| title | Novel transistor structures for future deep submicron MOS applications |
| title_full | Novel transistor structures for future deep submicron MOS applications |
| title_fullStr | Novel transistor structures for future deep submicron MOS applications |
| title_full_unstemmed | Novel transistor structures for future deep submicron MOS applications |
| title_short | Novel transistor structures for future deep submicron MOS applications |
| title_sort | novel transistor structures for future deep submicron mos applications |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits |
| url | https://hdl.handle.net/10356/41403 |
| work_keys_str_mv | AT thengahleong noveltransistorstructuresforfuturedeepsubmicronmosapplications |