Design of a low-voltage input-output rail-to-rail CMOS buffer
The objective of this project is to design a low-voltage rail-to-rail input/output CMOS buffer, which is able to work under a supply voltage of 1.8V typical and remain in operation even at l.2V or lower in the worst case for use in bond pad designs. The circuit is designed and simulated using Caden...
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| Format: | Thesis |
| Language: | English |
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2010
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| Online Access: | http://hdl.handle.net/10356/41770 |