Design of a low-voltage input-output rail-to-rail CMOS buffer
The objective of this project is to design a low-voltage rail-to-rail input/output CMOS buffer, which is able to work under a supply voltage of 1.8V typical and remain in operation even at l.2V or lower in the worst case for use in bond pad designs. The circuit is designed and simulated using Caden...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
2010
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/41770 |
| _version_ | 1826124807463239680 |
|---|---|
| author | Chai, Yanjie |
| author2 | Chen Tupei |
| author_facet | Chen Tupei Chai, Yanjie |
| author_sort | Chai, Yanjie |
| collection | NTU |
| description | The objective of this project is to design a low-voltage rail-to-rail input/output
CMOS buffer, which is able to work under a supply voltage of 1.8V typical and remain in operation even at l.2V or lower in the worst case for use in bond pad designs. The circuit is designed and simulated using Cadence Software. The process used is O.18um N-well CMOS single-poly six-metal layers. A low-voltage rail-to-rail input/output buffer is proposed, which combines a constant-gm rail-to-rail input stage and a compact rail-to-rail output stage with Class-AB configuration. The buffer can work effectively when the supply voltage change form 1.8V to 1.2V. The rail-to-rail operation has been achieved for input and output. The positive slew rate is 2.39V/us, and the negative slew rate is -2.32V/us. The following report demonstrates the design course of this project. The overall specifications achieved by this buffer are also presented at the end of this report. |
| first_indexed | 2024-10-01T06:26:24Z |
| format | Thesis |
| id | ntu-10356/41770 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:26:24Z |
| publishDate | 2010 |
| record_format | dspace |
| spelling | ntu-10356/417702023-07-04T15:27:39Z Design of a low-voltage input-output rail-to-rail CMOS buffer Chai, Yanjie Chen Tupei Siek Liter School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits The objective of this project is to design a low-voltage rail-to-rail input/output CMOS buffer, which is able to work under a supply voltage of 1.8V typical and remain in operation even at l.2V or lower in the worst case for use in bond pad designs. The circuit is designed and simulated using Cadence Software. The process used is O.18um N-well CMOS single-poly six-metal layers. A low-voltage rail-to-rail input/output buffer is proposed, which combines a constant-gm rail-to-rail input stage and a compact rail-to-rail output stage with Class-AB configuration. The buffer can work effectively when the supply voltage change form 1.8V to 1.2V. The rail-to-rail operation has been achieved for input and output. The positive slew rate is 2.39V/us, and the negative slew rate is -2.32V/us. The following report demonstrates the design course of this project. The overall specifications achieved by this buffer are also presented at the end of this report. Master of Science (Integrated Circuit Design) 2010-08-11T08:34:33Z 2010-08-11T08:34:33Z 2009 2009 Thesis http://hdl.handle.net/10356/41770 en 116 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Chai, Yanjie Design of a low-voltage input-output rail-to-rail CMOS buffer |
| title | Design of a low-voltage input-output rail-to-rail CMOS buffer |
| title_full | Design of a low-voltage input-output rail-to-rail CMOS buffer |
| title_fullStr | Design of a low-voltage input-output rail-to-rail CMOS buffer |
| title_full_unstemmed | Design of a low-voltage input-output rail-to-rail CMOS buffer |
| title_short | Design of a low-voltage input-output rail-to-rail CMOS buffer |
| title_sort | design of a low voltage input output rail to rail cmos buffer |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/41770 |
| work_keys_str_mv | AT chaiyanjie designofalowvoltageinputoutputrailtorailcmosbuffer |