Investigation of design techniques to reduce glitches for low power

This dissertation proposes and evaluates several glitch reduction techniques in the design of low power static CMOS circuits.

Podrobná bibliografie
Hlavní autor:	Foo, Chee Yin.
Další autoři:	Jong, Ching Chuen
Médium:	Diplomová práce
Vydáno:	2008
Témata:	DRNTU::Engineering::Electrical and electronic engineering::Power electronics
On-line přístup:	http://hdl.handle.net/10356/4251

Internet

http://hdl.handle.net/10356/4251