Investigation of design techniques to reduce glitches for low power

This dissertation proposes and evaluates several glitch reduction techniques in the design of low power static CMOS circuits.

Bibliographic Details
Main Author:	Foo, Chee Yin.
Other Authors:	Jong, Ching Chuen
Format:	Thesis
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Power electronics
Online Access:	http://hdl.handle.net/10356/4251

Internet

http://hdl.handle.net/10356/4251