Median filtering for image denoising with FPGA implementation
In this thesis, FPGA is chosen as the implementation platform based on an XSV-800 Virtex prototyping board from XESS Corporation. The focus of this thesis consists of three main parts: image acquisition, median filtering and image display, as well as two auxiliary parts.
Hovedforfatter: | |
---|---|
Andre forfattere: | |
Format: | Thesis |
Udgivet: |
2008
|
Fag: | |
Online adgang: | http://hdl.handle.net/10356/4305 |