Median filtering for image denoising with FPGA implementation
In this thesis, FPGA is chosen as the implementation platform based on an XSV-800 Virtex prototyping board from XESS Corporation. The focus of this thesis consists of three main parts: image acquisition, median filtering and image display, as well as two auxiliary parts.
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| Format: | Thesis |
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2008
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| Online Access: | http://hdl.handle.net/10356/4305 |