Process integration issues in the development of 0.18um 1.8v LP SRAM using local interconnect
This dissertation presents the development issues encountered during the present development of 0.18um LP (low-power) SRAM in Chartered Semiconductor Manufacturing Lid. All integration issues are explained with data and cross-sectional scanning electron micrographs for better explanation
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| Format: | Thesis |
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2008
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| Online Access: | http://hdl.handle.net/10356/4553 |