Design of ultra-low power asynchronous-logic quasi-delay-insensitive circuit templates

Design of ultra-low power asynchronous-logic quasi-delay-insensitive circuit templates

This report presents the design of Ultra-low power asynchronous Quasi-Delay-Insensitive (QDI) library cells and circuits templates using the CMOS 65nm Bulk process technology. Asynchronous systems are self-timed circuits that employ hand-shaking protocols instead of relying on a global clock to comm...

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Bibliografski detalji
Glavni autor: Chng, Clive Kuan Nee.
Daljnji autori: Gwee Bah Hwee
Format: Final Year Project (FYP)
Jezik:English
Izdano: 2011
Teme:
DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online pristup:http://hdl.handle.net/10356/45915

Internet

http://hdl.handle.net/10356/45915

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