Enhanced low-power high-speed probabilistic adders for error-toerant application
In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. To overcome all the possible errors is a very expensive task. It not only consumes a lot of power but also degrades the speed performance. With the concept of “error-tolerant” (ET), which allows the existence of...
| Հիմնական հեղինակ: | |
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| Այլ հեղինակներ: | |
| Ձևաչափ: | Թեզիս |
| Լեզու: | English |
| Հրապարակվել է: |
2011
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| Խորագրեր: | |
| Առցանց հասանելիություն: | https://hdl.handle.net/10356/46273 |