Design of high-speed low-power clock and data recovery circuit
In this thesis, the design of fully integrated high-speed low-power clock and data recovery (CDR) circuits in complementary metal-oxide-semiconductor (CMOS) devices for synchronous optical network (SONET) applications has been explored.
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| Format: | Thesis |
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2008
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| Online Access: | https://hdl.handle.net/10356/4801 |