Design of low-power and low-voltage VLSI multipliers

This thesis proposes several designs for low-power low-voltage digital CMOS multipliers for two's complement multiplication.

Bibliographic Details
Main Author:	Ong, Geok Ling.
Other Authors:	Liu, Po-Ching
Format:	Thesis
Published:	2008
Subjects:	DRNTU::Engineering::Electrical and electronic engineering::Electronic circuits
Online Access:	http://hdl.handle.net/10356/4997

Internet

http://hdl.handle.net/10356/4997