Design of low-power and low-voltage VLSI multipliers

This thesis proposes several designs for low-power low-voltage digital CMOS multipliers for two's complement multiplication.

书目详细资料
主要作者: Ong, Geok Ling.
其他作者: Liu, Po-Ching
格式: Thesis
出版: 2008
主题:
在线阅读:http://hdl.handle.net/10356/4997