Watermark insertion and detection through embedded test machine for VLSI IP protection
IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each havi...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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2012
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| Online Access: | http://hdl.handle.net/10356/50141 |