Watermark insertion and detection through embedded test machine for VLSI IP protection
IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each havi...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2012
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/50141 |
| _version_ | 1826130081912717312 |
|---|---|
| author | Che, Xuerong. |
| author2 | Chang Chip Hong |
| author_facet | Chang Chip Hong Che, Xuerong. |
| author_sort | Che, Xuerong. |
| collection | NTU |
| description | IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each having a constant number of flip-flops. Watermark bits are inserted by incorporating the test function into each component. This method of decomposing a large machine into small components and incorporating testability in each component substantially reduces the time complexity of synthesis. The algorithm is verified and the partition is implemented in C++ program. |
| first_indexed | 2024-10-01T07:50:43Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/50141 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:50:43Z |
| publishDate | 2012 |
| record_format | dspace |
| spelling | ntu-10356/501412023-07-07T16:54:03Z Watermark insertion and detection through embedded test machine for VLSI IP protection Che, Xuerong. Chang Chip Hong School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits IP watermarking is an efficient and economical approach to IP protection. In this project, a rather simple testability-driven partitioning method for large gate-level circuits is used for watermarking. The algorithm decomposes a single machine into an interconnection of component machines, each having a constant number of flip-flops. Watermark bits are inserted by incorporating the test function into each component. This method of decomposing a large machine into small components and incorporating testability in each component substantially reduces the time complexity of synthesis. The algorithm is verified and the partition is implemented in C++ program. Bachelor of Engineering 2012-05-30T04:14:05Z 2012-05-30T04:14:05Z 2012 2012 Final Year Project (FYP) http://hdl.handle.net/10356/50141 en Nanyang Technological University 72 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Che, Xuerong. Watermark insertion and detection through embedded test machine for VLSI IP protection |
| title | Watermark insertion and detection through embedded test machine for VLSI IP protection |
| title_full | Watermark insertion and detection through embedded test machine for VLSI IP protection |
| title_fullStr | Watermark insertion and detection through embedded test machine for VLSI IP protection |
| title_full_unstemmed | Watermark insertion and detection through embedded test machine for VLSI IP protection |
| title_short | Watermark insertion and detection through embedded test machine for VLSI IP protection |
| title_sort | watermark insertion and detection through embedded test machine for vlsi ip protection |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/50141 |
| work_keys_str_mv | AT chexuerong watermarkinsertionanddetectionthroughembeddedtestmachineforvlsiipprotection |