New architectures of multiplier and inner-product processor for high-speed on-chip serial-link bus
Research activities in bit-serial arithmetic circuits have been saturated in recent years due to the unprecedented throughput demand in today's electronic applications that is difficult to achieve even by the parallel counterparts. In addition, the area advantage of serial architecture is becom...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
2013
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/52489 |