Low temperature three dimensional wafer level copper thermo-compression bonding
As semiconductor technology scales, integrated circuit performance is shifting from device limited to interconnect limited. Interconnect delay is unavoidably worsen due to longer, thinner interconnect wire and tighter pitch. Three dimensional (3D) integration provides a simple solution to alleviate...
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| Format: | Thesis |
| Language: | English |
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2013
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| Online Access: | http://hdl.handle.net/10356/52550 |