Design a power-efficient asyncrhonous logic quasi-delay-insensitive network-on-chip for multi-core processor
This report pertains to the design of a power-efficient asynchronous logic quasi-delay-insensitive (QDI) Network-on-Chip (NoC) for multi-core processor. To achieve the low power requirement, the proposed NoC is designed to operate in the sub-threshold region. However, operating in the deep sub-thres...
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| Format: | Final Year Project (FYP) |
| Language: | English |
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2013
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| Online Access: | http://hdl.handle.net/10356/53110 |