Design and implementation of a digital integrated circuit for data transfer using VHDL
A final year project is a core module of School of Electrical and Electronic Engineering in partial fulfillment of the requirements for the degree of Bachelor of Engineering. This report details the tasks performed and the experience gained by the author during his final year working on this project...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2013
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/53400 |