Leakage reduction techniques for submicron CMOS circuits
Leakage current has become a significant problem in sub-micron circuits due to the continuous scaling of channel length. Therefore, leakage reduction has become an essential design process in order to achieve a better performance especially in low power circuit applications. Leakage cont...
| Κύριος συγγραφέας: | |
|---|---|
| Άλλοι συγγραφείς: | |
| Μορφή: | Final Year Project (FYP) |
| Γλώσσα: | English |
| Έκδοση: |
2013
|
| Θέματα: | |
| Διαθέσιμο Online: | http://hdl.handle.net/10356/54459 |
| Περίληψη: | Leakage current has become a significant problem in sub-micron circuits due to the
continuous scaling of channel length. Therefore, leakage reduction has become an
essential design process in order to achieve a better performance especially in low
power circuit applications.
Leakage control can be achieved by process design and circuit design. Both of these
design techniques are introduced in this project with focus on circuit design
techniques. Simulations will be carried out on 65nm process transistors using
Cadence software to investigate the performances of these techniques. The results
provided will serve as a guideline in understanding the pros and cons of these circuit
design techniques, which are proved to be effective. |
|---|