A study of the electronic properties of III-V compound semiconductor integrated with silicon
This thesis presents systematic studies on monolithic heteroepitaxial integration of III-V compound semiconductor on Si substrate employing the graded Si1-xGex buffer layer. One of the essential growth procedures for antiphase boundary free GaAs/Ge growth is the pre-growth high-temperature in-situ a...
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| Format: | Thesis |
| Language: | English |
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2014
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| Online Access: | http://hdl.handle.net/10356/60691 |
| _version_ | 1811692560624648192 |
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| author | Chen, Kah Pin |
| author2 | Yoon Soon Fatt |
| author_facet | Yoon Soon Fatt Chen, Kah Pin |
| author_sort | Chen, Kah Pin |
| collection | NTU |
| description | This thesis presents systematic studies on monolithic heteroepitaxial integration of III-V compound semiconductor on Si substrate employing the graded Si1-xGex buffer layer. One of the essential growth procedures for antiphase boundary free GaAs/Ge growth is the pre-growth high-temperature in-situ annealing of a Ge surface coupling with the use of a 6o off-cut Si substrate. Besides, a study was performed to examine the impact of various GaAs buffer thicknesses on the electrical characteristics of GaAs grown on the hetero-substrate. Furthermore, an in-depth study of the dependence of electrical characteristics on proximity to the GaAs/Ge heterointerface was performed using deep-level transient spectroscopy analysis. Lastly, AlGaAs/GaAs heterojunction bipolar transistors were grown on the Ge/graded-Si1-xGex/Si hetero-substrate to demonstrate the viability of this integrated platform. A correlation between the DC characteristics, especially offset voltage and deep-level traps behavior in the GaAs layer, were discussed. |
| first_indexed | 2024-10-01T06:37:44Z |
| format | Thesis |
| id | ntu-10356/60691 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:37:44Z |
| publishDate | 2014 |
| record_format | dspace |
| spelling | ntu-10356/606912020-11-01T11:33:07Z A study of the electronic properties of III-V compound semiconductor integrated with silicon Chen, Kah Pin Yoon Soon Fatt School of Electrical and Electronic Engineering Singapore-MIT Alliance Programme DRNTU::Engineering::Materials This thesis presents systematic studies on monolithic heteroepitaxial integration of III-V compound semiconductor on Si substrate employing the graded Si1-xGex buffer layer. One of the essential growth procedures for antiphase boundary free GaAs/Ge growth is the pre-growth high-temperature in-situ annealing of a Ge surface coupling with the use of a 6o off-cut Si substrate. Besides, a study was performed to examine the impact of various GaAs buffer thicknesses on the electrical characteristics of GaAs grown on the hetero-substrate. Furthermore, an in-depth study of the dependence of electrical characteristics on proximity to the GaAs/Ge heterointerface was performed using deep-level transient spectroscopy analysis. Lastly, AlGaAs/GaAs heterojunction bipolar transistors were grown on the Ge/graded-Si1-xGex/Si hetero-substrate to demonstrate the viability of this integrated platform. A correlation between the DC characteristics, especially offset voltage and deep-level traps behavior in the GaAs layer, were discussed. Doctor of Philosophy (AMM and NS) 2014-05-29T06:02:31Z 2014-05-29T06:02:31Z 2011 2011 Thesis http://hdl.handle.net/10356/60691 en 157 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Materials Chen, Kah Pin A study of the electronic properties of III-V compound semiconductor integrated with silicon |
| title | A study of the electronic properties of III-V compound semiconductor integrated with silicon |
| title_full | A study of the electronic properties of III-V compound semiconductor integrated with silicon |
| title_fullStr | A study of the electronic properties of III-V compound semiconductor integrated with silicon |
| title_full_unstemmed | A study of the electronic properties of III-V compound semiconductor integrated with silicon |
| title_short | A study of the electronic properties of III-V compound semiconductor integrated with silicon |
| title_sort | study of the electronic properties of iii v compound semiconductor integrated with silicon |
| topic | DRNTU::Engineering::Materials |
| url | http://hdl.handle.net/10356/60691 |
| work_keys_str_mv | AT chenkahpin astudyoftheelectronicpropertiesofiiivcompoundsemiconductorintegratedwithsilicon AT chenkahpin studyoftheelectronicpropertiesofiiivcompoundsemiconductorintegratedwithsilicon |