Low power dual mode CMOS logic
The recently proposed dual mode logic (DML) gates family enables a very high level of energy-delay optimization flexibility at the gate level. In this paper,this novel high speed and low power dual mode logic is presented.the presented logic family can be switched between static and dynamic modes of...
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| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2014
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| Online Access: | http://hdl.handle.net/10356/61339 |