Low power 16-bit multiplier design
The aim of this project is to investigate the design of different 16-bit CMOS Multiplier based on different logic and its implementation for portable low power applications. Arithmetic circuits such as digital adders and multipliers are used extensively in digital signal processor for filtering appl...
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| Other Authors: | |
| Format: | Final Year Project (FYP) |
| Language: | English |
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2015
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| Online Access: | http://hdl.handle.net/10356/62023 |
| _version_ | 1826109763236134912 |
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| author | Heng, Zeng An |
| author2 | Gwee Bah Hwee |
| author_facet | Gwee Bah Hwee Heng, Zeng An |
| author_sort | Heng, Zeng An |
| collection | NTU |
| description | The aim of this project is to investigate the design of different 16-bit CMOS Multiplier based on different logic and its implementation for portable low power applications. Arithmetic circuits such as digital adders and multipliers are used extensively in digital signal processor for filtering applications. In a digital multiplier, the addition of the partial products is normally carried out by a group of Half-Adders and Full-Adders. To reduce the delay and power dissipation of the multiplier, a 4-to-2 adder (comprises 2 Full-Adders) has recently been proposed to perform the partial product additions. In this project, the 16-bit CMOS multipliers architecture based on different types of adders will be investigated and developed using the VHDL code. The appropriate parameter values will be determined through behavioural simulations. The design could then be implemented into a FPGA for functional evaluation. Students will learn knowledge in IC design, Hspice, and VHDL code. |
| first_indexed | 2024-10-01T02:23:36Z |
| format | Final Year Project (FYP) |
| id | ntu-10356/62023 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:23:36Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/620232023-07-07T16:41:37Z Low power 16-bit multiplier design Heng, Zeng An Gwee Bah Hwee School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits The aim of this project is to investigate the design of different 16-bit CMOS Multiplier based on different logic and its implementation for portable low power applications. Arithmetic circuits such as digital adders and multipliers are used extensively in digital signal processor for filtering applications. In a digital multiplier, the addition of the partial products is normally carried out by a group of Half-Adders and Full-Adders. To reduce the delay and power dissipation of the multiplier, a 4-to-2 adder (comprises 2 Full-Adders) has recently been proposed to perform the partial product additions. In this project, the 16-bit CMOS multipliers architecture based on different types of adders will be investigated and developed using the VHDL code. The appropriate parameter values will be determined through behavioural simulations. The design could then be implemented into a FPGA for functional evaluation. Students will learn knowledge in IC design, Hspice, and VHDL code. Bachelor of Engineering 2015-01-06T02:46:16Z 2015-01-06T02:46:16Z 2014 2014 Final Year Project (FYP) http://hdl.handle.net/10356/62023 en Nanyang Technological University 111 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Heng, Zeng An Low power 16-bit multiplier design |
| title | Low power 16-bit multiplier design |
| title_full | Low power 16-bit multiplier design |
| title_fullStr | Low power 16-bit multiplier design |
| title_full_unstemmed | Low power 16-bit multiplier design |
| title_short | Low power 16-bit multiplier design |
| title_sort | low power 16 bit multiplier design |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/62023 |
| work_keys_str_mv | AT hengzengan lowpower16bitmultiplierdesign |