Investigation of interconnect layout on CU/Low-K TDDB reliability
Traditionally, conventional test structures and standard voltage biasing is used for the accelerated TDDB testing. However, the standard layout and bias conditions used are not representative of the actual circuit. Hence, in this project the influence of layout and biasing of the test structure on T...
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| Format: | Thesis |
| Language: | English |
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2015
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| Online Access: | https://hdl.handle.net/10356/62521 |