Low power performance analysis of CMOS arithmetic units
The dissertation takes into study of ultra-low power methodologies by analyzing full adders constructed with different topologies. Full adders are at the heart of multiple larger circuits which includes multipliers, shifters, data compressors for signal encoding, DSP architectures and ALU which in t...
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| Format: | Thesis |
| Language: | English |
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2016
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| Online Access: | http://hdl.handle.net/10356/66426 |