Low power performance analysis of CMOS arithmetic units
The dissertation takes into study of ultra-low power methodologies by analyzing full adders constructed with different topologies. Full adders are at the heart of multiple larger circuits which includes multipliers, shifters, data compressors for signal encoding, DSP architectures and ALU which in t...
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| Other Authors: | |
| Format: | Thesis |
| Language: | English |
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2016
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| Online Access: | http://hdl.handle.net/10356/66426 |
| _version_ | 1811696907185029120 |
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| author | Moni, Bhaskar |
| author2 | Kim Teen Lau |
| author_facet | Kim Teen Lau Moni, Bhaskar |
| author_sort | Moni, Bhaskar |
| collection | NTU |
| description | The dissertation takes into study of ultra-low power methodologies by analyzing full adders constructed with different topologies. Full adders are at the heart of multiple larger circuits which includes multipliers, shifters, data compressors for signal encoding, DSP architectures and ALU which in tum is a major component of the CPU.
hi this dissertation, eight different topologies have been analyzed to construct a 1-bit full adder and their performance on the basis of average power consumption, delay and power-delay product has been studied over a voltage range of 900mV to 1.2 V supply voltage and a frequency range of 250 MHz to 1 GHz. The circuits remain functional to voltages as low as 600 mV but the powerless and groundless circuits[22] falter under so low an operating voltage. Added to that the specified operating range by TSMC for the 65 nm technology node is 900 mV to 1.2 V.
Out of them, two topologies are selected based on the values of performance parameters such as delay, average power consumption and power delay product to create a three stage 8:2 “lossy” compressor and after that their performance characteristics are also studied.
The circuits are simulated in Cadence virtuoso software using TSMC’s 65nm process foundry technology and the results show that the transmission gate topology is the best one considering the measured aspects of the circuits but dynamic logic cannot be neglected owing to it being flexible as in it can switched on and off with the help of a control signal favoring its presence in various electronics equipment. |
| first_indexed | 2024-10-01T07:46:49Z |
| format | Thesis |
| id | ntu-10356/66426 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:46:49Z |
| publishDate | 2016 |
| record_format | dspace |
| spelling | ntu-10356/664262023-07-04T15:03:40Z Low power performance analysis of CMOS arithmetic units Moni, Bhaskar Kim Teen Lau School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering The dissertation takes into study of ultra-low power methodologies by analyzing full adders constructed with different topologies. Full adders are at the heart of multiple larger circuits which includes multipliers, shifters, data compressors for signal encoding, DSP architectures and ALU which in tum is a major component of the CPU. hi this dissertation, eight different topologies have been analyzed to construct a 1-bit full adder and their performance on the basis of average power consumption, delay and power-delay product has been studied over a voltage range of 900mV to 1.2 V supply voltage and a frequency range of 250 MHz to 1 GHz. The circuits remain functional to voltages as low as 600 mV but the powerless and groundless circuits[22] falter under so low an operating voltage. Added to that the specified operating range by TSMC for the 65 nm technology node is 900 mV to 1.2 V. Out of them, two topologies are selected based on the values of performance parameters such as delay, average power consumption and power delay product to create a three stage 8:2 “lossy” compressor and after that their performance characteristics are also studied. The circuits are simulated in Cadence virtuoso software using TSMC’s 65nm process foundry technology and the results show that the transmission gate topology is the best one considering the measured aspects of the circuits but dynamic logic cannot be neglected owing to it being flexible as in it can switched on and off with the help of a control signal favoring its presence in various electronics equipment. Master of Science (Electronics) 2016-04-05T07:40:45Z 2016-04-05T07:40:45Z 2016 Thesis http://hdl.handle.net/10356/66426 en 110 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Moni, Bhaskar Low power performance analysis of CMOS arithmetic units |
| title | Low power performance analysis of CMOS arithmetic units |
| title_full | Low power performance analysis of CMOS arithmetic units |
| title_fullStr | Low power performance analysis of CMOS arithmetic units |
| title_full_unstemmed | Low power performance analysis of CMOS arithmetic units |
| title_short | Low power performance analysis of CMOS arithmetic units |
| title_sort | low power performance analysis of cmos arithmetic units |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | http://hdl.handle.net/10356/66426 |
| work_keys_str_mv | AT monibhaskar lowpowerperformanceanalysisofcmosarithmeticunits |