Ultra low power asynchronous-logic quasi-delay-insensitive circuit design
This thesis pertains to the investigation of low power, high robustness and yet speed-efficient digital electronics for portable/mobile/secured applications. We adopt the esoteric asynchronous-logic (async) vis-à-vis the conventional synchronous-logic (sync); more specifically, the async quasi-delay...
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| Format: | Thesis |
| Language: | English |
| Published: |
2016
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| Online Access: | http://hdl.handle.net/10356/68838 |